Linux, Rt, Uds, SOME IP, SecOC, Canoe, MISRA C++, CI CD, CAN-FD, Rca, Observability-led Validation, Vector DaVinci, TSN, Autosar, DDS, SafeRTOS, ETAS ISOLAR, ISO 26262, ISO 21434, ARXML, Secure Boot

boundary scan , Jtag, Scripting, Tcl, multi-clock domain designs, DFT signoff, scan architecture, MBIST, DFT architecture, Timing Constraints, ATPG, clocking architectures, silicon bring-up, LBIST, manufacturing test flows, compression methodologies

Validation Testing, Virtual simulation, Data acquisition systems, Dfmea, Benchmarking, Process Fmea

SAP Document and Reporting Compliance (DRC), Revenue Accounting and Reporting (RAR), Idocs, Apis, Profit Center Accounting, Asset Accounting, Material Ledger, Cost Center Accounting, margin analysis, COPA, Parallel Ledgers, Financial Close, Accounts Receivable, Accounts Payable, Universal Journal, Product Costing, Group Reporting, SAP Integration Suite, Intercompany Accounting, General Ledger, SAP S/4HANA Finance

arinc 429 , ni labview , C#, Agile Methodologies, Tortoisesvn, Can, Python, structural coverage analysis, Polarion, AFDX, Time-Triggered Protocol, IBM DOORS, Synergy, black-box integration testing, model coverage analysis, DO-178B C, timing margin analysis

synopsys primetime , Perl, Python, Tcl, Unified Power Format UPF, Tweaker, Constraints Validation Synopsys TCM GCA Ausdia TimeVision SpyGlass Constraints, Cadence CCD, Sign-off STA Synopsys PrimeTime PT PT-PX, PrimeClosure, Cadence Tempus, Synopsys Formality, Timing Closure ECO Cadence Tempus

static timing analysis, LINT, Logic Synthesis, cdc, formal verification, Dft, Cadence-based ASIC design environments, low-power design methodologies, micro-architecture development, SystemVerilog RTL design

Java, React, Spring Boot, Safe Agile, AWS, Oracle 19c