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We are looking for talented Analog Layout Engineers with strong experience in advanced FinFET technologies to join a leading semiconductor project for a global client.
Key Requirements
✅5-8 years of relevant Analog Layout experience
✅ Expertise in FinFET technologies (7nm / 3nm)
✅ Strong understanding of Analog/Mixed Signal Layout concepts
✅ Experience working on advanced node designs and physical implementation
✅ Candidates from non-Intel client projects preferred
Additional Information
Job ID: 152532431
Skills:
Analog and Analog Circuits fundamentals, Circuit Design concepts, Layout Design for standard cells, CMOS process design rules
Skills:
Analog Mixed-Signal Layout, MOS resistor capacitor current mirror differential pair and analog IP layouts, DRC LVS ERC and PEX, advanced matching and layout techniques, Cadence Virtuoso Custom Compiler, FinFET advanced-node layout, lower-node technologies
Skills:
Routing, Pvs, PERL, Tcl, R3D, PEX, LVS, Layout Techniques, Verification, Skill Programming, CAD Tools, Calibre, Analog Layout, ERC, VCAR, DRC, VSR, virtuoso
Skills:
MATLAB, Python, post-layout extraction, layout techniques, ADE, Monte Carlo analysis, CMOS analog design, Spectre, mixed-signal IC design, Cadence Virtuoso, Verilog-A modeling, corner simulations