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Role Overview
The Front-End Lead Engineer will drive the design, development, and signoff of high-performance digital IP blocks and subsystems while leading Functional ECO implementation at the netlist level. This role requires strong technical leadership across the front-end design flow, including RTL development, verification of coordination, synthesis, signoff, and Functional ECO execution. You will collaborate with cross-functional teams, ensure design quality, and mentor junior engineers to build technical depth within the organization.
Key Responsibilities
Front-End Design & Signoff
• Drive design signoff activities: lint, CDC/RDC, synthesis
• Lead the front-end development of digital IP blocks or subsystems from concept to implementation.
• Collaborate with architects, verification, physical design, firmware/software teams, and program managers.
• Support P&R and signoff teams with RTL fixes, constraints, and ECO requirements.
Team & Project Leadership
• Own schedules, deliverables, and quality for the front-end engineering team.
• Mentor junior engineers in RTL design, ECO implementation, verification practices, and signoff flows.
• Drive continuous improvement of front-end methodologies, automation, and best practices.
Required Skills
• Strong hands-on experience across ASIC front-end design flow.
• Exposure Functional ECO flows using Synopsys Formality ECO and/or Cadence Conformal ECO.
• Proficiency in Verilog/System Verilog, gate-level netlist editing, and scripting (TCL, Perl, Python).
• Solid understanding of timing analysis, STA constraints, and physical design interactions.
• Strong background in formal verification, simulation, debugging, and issue closure.
• Excellent analytical and problem-solving skills with attention to quality and detail.
Preferred Qualifications
• Bachelor's or Master's degree in Electrical/Electronics Engineering.
• Strong foundation in digital design principles and problem-solving skills.
RequirementsYears of Experience: 6–8 Years
Preferred Qualifications
• Bachelor's or Master's degree in Electrical/Electronics Engineering.
• Strong foundation in digital design principles and problem-solving skills.
Job ID: 150657089
Skills:
power optimization , Static Timing Analysis, power analysis, low power design techniques, SoC integration, Design-for-Test, constraints development for Physical Design implementation, Design-for-Debug, SoC Debug architectures
Skills:
Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC
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