RTL Design Engineer
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Job Title - RTL Design Engineers
Exp Level: 4+ yrs
Loctaion: Hyderabad /Bangalore
Job Description:
• RTL coding knowledge
• Top-level (SOC) level basic industry standard Arch knowledge
• SoC & IP level Integration knowledge
• IPXACT knowledge
• IORING and Phys & GPIOs basic functionality
• Design Partitioning(Tilification) knowledge
• Design RTL quality checks:
• Tools knowledge:
• Design and scripting languages:
Interested can share CV to [Confidential Information]
Job ID: 153635463
Skills:
Verilog, LINT, Synthesis, spyglass, cdc, RDC, Timing, Ethernet protocols IP, PPA optimization, RTL optimization, systemverilog
Skills:
Perl, Verilog, Python, Makefiles, RTL Build flows, Chip Design Functions, SoC Verification, Physical Design, Rtl Design, Dft, Synthesis, System-On-Chip design implementation flow
Skills:
Perl, Verilog, Python, Tcl, Rtl Design, Ethernet IPs, VHDL, AXI Protocols, Ethernet protocol
Skills:
Tcp Ip, Pcie, Perl, Shell scripting, Ethernet, RDMA IPs, VCS simulation tool, Silicon IP development process methodologies, Verilog RTL design, Design for Test methodologies, DMAs, NVMe based Storage IP
Skills:
Automation Frameworks, Sta, LINT, Memory operation, Synchronous design concepts, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, spyglass, Synthesis, device physics, CDC methodologies
