RTL Design Engineer

conformal lec , Perl, Verilog, Python, Tcl, VC spyglass, IPXACT, IORING, LINT, Formality, VSI, UPF, Design Partitioning, Phys GPIOs, SoC IP level Integration, RTL Coding

Verilog, LINT, Synthesis, spyglass, cdc, RDC, Timing, Ethernet protocols IP, PPA optimization, RTL optimization, systemverilog

Perl, Verilog, Python, Makefiles, RTL Build flows, Chip Design Functions, SoC Verification, Physical Design, Rtl Design, Dft, Synthesis, System-On-Chip design implementation flow

Tcp Ip, Pcie, Perl, Shell scripting, Ethernet, RDMA IPs, VCS simulation tool, Silicon IP development process methodologies, Verilog RTL design, Design for Test methodologies, DMAs, NVMe based Storage IP

Automation Frameworks, Sta, LINT, Memory operation, Synchronous design concepts, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, spyglass, Synthesis, device physics, CDC methodologies