boundary scan , C, Perl, Verilog, System Verilog, Python, Tcl, Memory BIST, IEEE1687, Fishtail, IEEE1500, DFT RTL generation, IEEE1149.1, ATPG SAF, Spyglass DFT, VHDL, MBIST verification, ATPG, TDF, Spyglass LINT

Perl, Python, Dft, SV, coverage metrics, Profiling Tools, Uvm, X prop, constrained random testing

Debugging, occ, ICL, Dft, DRC coverage, pdl, Scan ATPG, Simulation, IJTAG, SSN

Python, Perl, Dft, Uvm, SV, Profiling Tools, constrained random testing, coverage metrics

Verilog, Jtag, Dft, MBIST, IEEE1500, IEEE1687, ATPG, Cadence

DFT architecture, ATPG setup, digital design fundamentals, hierarchical DFT methodologies, silicon bring-up, JTAG simulation, SCAN solutions, DFT scripting automation, post-silicon debug