Scan Compression Techniques, Fault Models, DFT Tools, Sign-Off, Scripting Automation, DFT Implementation, Boundary Scan IEEE 1149.1, Test Coverage Optimization, Post-Silicon Validation

Gate Level Simulations, stuck-at transition, Scan Insertion, memory repair solutions, MBIST, JTAG boundary scan, bridge path delay, DFT architecture, EDA Tools, DRC, IEEE 1149.1, ATPG pattern generation, scan chain stitching, DFT rule checks

Python, Perl, Logic Design, Uvm, Post Silicon Testing, SV, DFT Engineering, Architecture Verification, Constrained random testing, Profiling Tools, Coverage metrics

Unix, Svn, Shell, Report Automation, Linux, Verilog, Tcl, Python, Perl, Git, Cadence Modus, MBIST, Scan compression, Scan architecture, log parsing, TestMAX, systemverilog, ATPG, DFT fundamentals, TetraMax, Synopsys DFT Compiler, LBIST, flow orchestration

retargeting , boundary scan , DFT architecture, pattern generation validation, MBIST, EDT OCC integration, Boundary Scan JTAG, Scan Architecture, IJTAG, DFT implementation debug, scan implementation, Memory IP Test Simulations

boundary scan , logic bist , Test Automation, DFT Methodologies, Scan Design, Fault Simulation, ATE Programming, Design Debugging, DFT Architecture, Timing Analysis

Scan, scripting skills in Perl, tessent DFT, DFT architecture definition, HDLs, Genus, MBIST, Cadence digital implementation tools, Tempus, JTAG boundary scan, ATPG flow implementation

simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, leading DFT activities, IP integration, DFT specification definition, SoC cycles, silicon debug activities