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Design Verification Engineer
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- Posted 8 days ago
- Be among the first 50 applicants
Job Description
Role : Design Verification Engineer
Work Location : Bangalore
Exp : 5+ Years
Industry : Semiconductor
Description
We are seeking a skilled Design Verification Engineer to join our team in India. The ideal candidate will have a strong background in design verification and a passion for ensuring the quality and reliability of complex systems.
Responsibilities
- Develop and execute design verification plans and test cases for complex systems.
- Analyze requirements and specifications to create comprehensive verification strategies.
- Collaborate with design and development teams to resolve issues and ensure quality.
- Utilize verification tools and methodologies to automate testing processes.
- Document test results and provide detailed reports on verification outcomes.
- Participate in design reviews and provide feedback based on verification results.
Skills and Qualifications
- Bachelor's or Master's degree in Electronics, Computer Science, or a related field.
- 5-12 years of experience in design verification or validation, preferably in semiconductor or embedded systems.
- Strong knowledge of verification methodologies such as UVM, OVM, or similar frameworks.
- Proficiency in SystemVerilog, Verilog, or VHDL for hardware description and verification.
- Experience with scripting languages such as Python, Perl, or Tcl for automation.
- Familiarity with tools like ModelSim, QuestaSim, or similar for simulation and verification.
- Understanding of digital design concepts and ASIC/FPGA architecture.
- Excellent analytical and problem-solving skills, with attention to detail.
More Info
Key Skills
Verification Planning
Testbench Development
Functional Coverage
Debugging Skills
FPGA Verification
About Company
Skills:
code coverage , Verilog, Debugging, FPGA Design, Scripting, Regression Testing, Vcs, systemverilog, Uvm, Testbench Development, Simulation Tools, Functional Verification, Timing Analysis, SoC Verification, Verification Plan, Verdi
Early Applicant
Skills:
code coverage , perl, Regression Testing, Ovm, Ethernet Protocols, Python, multiple RTL simulators, X-propagation, Uvm, systemverilog, functional coverage
Skills:
Perl, Shell scripting, Python, vManager, Xcelium, Cadence environments, JasperGold, UVM methodologies
Skills:
SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification
Skills:
Perl, Python, Synopsys VCS, Cadence Xcelium, Uvm, systemverilog