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DFT Engineer
Experience - 5+years
Location- Bangalore/Hyderabad
Experience with Chip level DFT and Post Silicon debug / analysis
Understanding of DFT architectures like :
a. ATPG Pattern generation
b. ATPG coverage analysis
c. Pattern simulation ( both timing/no timing)
d. Pattern Retargeting
e. Understanding JTAG/IJTAG
f. MBIST and Logic BIST
Job ID: 149369797
Skills:
boundary scan , C, Perl, Verilog, System Verilog, Python, Tcl, Memory BIST, IEEE1687, Fishtail, IEEE1500, DFT RTL generation, IEEE1149.1, ATPG SAF, Spyglass DFT, VHDL, MBIST verification, ATPG, TDF, Spyglass LINT
Skills:
DFT verification, IEEE1149, CTL generation, MBIST, Scan, ASIC SoC designs, DFT validation, 1500, 1687, DFT EDA tools, Dft, timing generating test cases, Analog IPs, HSIOs, debugging GLS
Skills:
boundary scan , Technical Leadership, Perl, Python, Tcl, test compression, scan compression, DFT signoff, test access strategies, pattern optimization, DFT methodologies, MBIST, DFT architecture definition, Failure Analysis, ATPG, silicon bring-up, yield ramp, LBIST
Skills:
Perl, Python, Dft, SV, coverage metrics, Profiling Tools, Uvm, X prop, constrained random testing
Skills:
boundary scan , Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, Tessent tool sets, TestMax
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