Uart, Spi, Pcie, Verilog, I2c, Unix Systems, Otn, Uvm, Microsemi FPGAs, systemverilog, Ethernet-based protocols, quartus, VHDL, scripting tools, Vivado, VMM, AXI memory controllers, Libero

lattice , synplify , microblaze , DDR, Pcie, Verilog, Ethernet, Signal Processing, high-speed interfaces, Microsemi, IP integration, FPGA architecture, Rtl Design, VHDL, Verification, Intel Altera, embedded processors, digital design principles, Data Processing, Nios, Timing Analysis, systemverilog, quartus, hardware debugging, Vivado, Modelsim, Xilinx

FPGA Design, Static Timing Analysis, Synthesis, Timing Closure, systemverilog, Code coverage analysis, RTL design using Verilog

random testing , Oops, Fpga, Pcie, Verilog, System Verilog, coverage assertions, Debug, Ethernet based protocols, VCS simulation flow, Otn, Uvm, VMM, AXI memory controllers, adversarial testing

Intel/ Altera development tool chains, FPGA Design, cdc, Reverse Engineering, test bench for verification, RTL design using VHDL/verilog, Design of IP cores-protocols-HDLC-SPI, STA and other timing considerations

memory controllers , Uart, Spi, Hdl Languages, Pcie, Verilog, I2c, Unix Systems, Otn, Uvm, Microsemi FPGAs, systemverilog, Ethernet-based protocols, Axi, quartus, VHDL, scripting tools, Vivado, VMM, Libero

FPGA Design, Verilog, systemverilog, Xilinx Vivado, altera quartus, Peripheral Protocols