ASIC Engineer, Design Verification
ASIC Engineer, Design Verification
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- Posted 28 days ago
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Job Description
- Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
- Develop functional tests based on verification test plan
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
- Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry
Minimum Qualifications
- Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience of at least 9+ years
- Track record of first-pass success in ASIC development cycles
- Hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology
- Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
- Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation
- Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
- Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
- At least 9+ years of hands on experience
Preferred Qualifications
- Experience in development of UVM based verification environments from scratch
- Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs
- Experience with revision control systems like Mercurial(Hg), Git or SVN
- Experience with verification of ARM/RISC-V based sub-systems or SoCs
- Experience with IP or integration verification of high-speed interfaces like PCIe, DDR, Ethernet
- Experience working across and building relationships with cross-functional design, model and emulation teams
More Info
Job Type:
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Function:
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Key Skills
implement IP/SoC verification plans
C/C++
ASIC development cycles
About Company
Skills:
UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), C, C++, Shell, Pcie, Perl, Arm, Python, Tcl, Systemc, MCU, Hardware Emulation Platforms, RISC-V, UCIe, systemverilog, Verification Methodology, AMBA, Axi, Formal Model Equivalence Checking Tools, formal verification, VC Formal
Skills:
Perl, Python, Tcl, Xcelium simulation, vManager, Real-Number Modeling, Verilog-AMS, JasperGold, Uvm, SVA, systemverilog
Skills:
Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, ASIC Design, Power aware simulations, Verification, Validation, AHB
Skills:
python, Perl, System Verilog, DDR-IO verification, LPDDR JDEC specifications, Uvm, coverage driven verification methodology, LPDDR5
Skills:
Spi, Uart, I2c, Ethernet, Can, DV firmware verification, GLS, Uvm, Specman, systemverilog, AMS CDC digital verification, post-silicon verification, AHB, C-based SoC design verification, UPF based verification, CSI, CPF, cybersecurity processes, AI ML based DV, formal verification, APB, Axi, functional safety, PAGLS