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Job Description
Intellexe Management Consultants is hiring experienced DFT Engineers for an exciting opportunity with one of its esteemed clients. We are looking for candidates with strong technical expertise in DFT implementation, scan insertion, MBIST, ATPG, simulation, and SoC-level DFT activities.
If you have hands-on experience with industry-standard DFT tools and a strong understanding of test methodologies, this opportunity is for you!
Key Responsibilities & Technical Expertise
- DFT Fundamentals: BSCAN, MBIST, Scan, and ATPG.
- DFT Implementation: MBIST insertion, scan insertion, and ATPG pattern generation.
- Simulation & Debug: ATPG, MBIST, and BSCAN simulation, zero-delay simulation, and SDF timing simulation.
- DFT Tools: Siemens Tessent, Synopsys, and Cadence.
- Simulation Tools: VCS, NC-Sim, and Xcelium.
- Fault Models: Stuck-at faults, Transition Delay Faults (TDF), and IDDQ testing.
- Test Coverage: Scan test coverage improvement and fault coverage analysis.
- SoC-Level DFT: OCC/OPCG insertion, EDT/scan compression logic insertion, and clock module handling for scan.
- Post-Silicon & Production Testing: Silicon bring-up, production testing, tester debug, and Shmoo plot/graph analysis.
- Timing & Coordination: Test-mode timing constraints and coordination with STA and Physical Design (PD) teams.
Candidate Requirements
- 3–15 years of total professional experience, with relevant hands-on DFT experience.
- Strong understanding of DFT concepts, implementation methodologies, and test flows.
- Practical experience with relevant DFT and simulation tools.
- Ability to provide a detailed skill matrix specifying hands-on experience in years for each applicable technical skill.
More Info
Key Skills
About Company
About Recruiter
Jaipal Singh
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Skills:
Built-In Self-Test (BIST) implementation, Design for Testability (DFT), boundary scan standards, scan chain insertion and optimization techniques, silicon debug and failure analysis processes
Skills:
SSN LBIST, MBIST insertion simulation and debug on RTL and gates netlist, Verilog Hdl, At-Speed LBIST coverage analysis, STA DFT Test mode timing constraint development and analysis, Simulators and waveform debugging tools, Scan ATPG with SSN Stuck-At, Scripting with Perl Tcl, ATE silicon debug, Simulation and debug, Scan insertion with compression, Boundary Scan insertion simulation and verification
Skills:
boundary scan , Jtag, DFT verification, scan compression, Scan Insertion, DFT requirements, DFT simulation, pattern verification, MBIST, Cadence, DFT tool flows, DFT architecture, ATPG, gate-level simulation debug, silicon bring-up, Siemens EDA, Synopsys
Skills:
Scan Compression Techniques, Fault Models, DFT Tools, Sign-Off, Scripting Automation, DFT Implementation, Boundary Scan IEEE 1149.1, Test Coverage Optimization, Post-Silicon Validation
Skills:
Synthesis, ASIC SOC design flow, Scan Insertion, digital design fundamentals, JTAG Boundary Scan, ATPG, Scan Compression, MBIST, STA concepts, DFT Verification