C
DFT Engineer
C
DFT Engineer
Capgemini- Posted 2 days ago
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Job Description
Location: Bangalore / Hyderabad / Chennai/Pune
Experience: 12 Years
Job Description
We are seeking a highly motivated DFT Engineer to join our ASIC/SOC Design team. The candidate will be responsible for implementing and verifying DFT features to improve testability and manufacturing quality of complex SOC/ASIC designs.
Key Responsibilities
- Develop and implement DFT architecture for ASIC/SOC designs.
- Insert and verify Scan, MBIST, LBIST, Boundary Scan (JTAG), and Compression logic.
- Work on ATPG pattern generation and fault coverage analysis.
- Perform DFT verification, simulation, and debugging.
- Collaborate with Design, Verification, Physical Design, and Test teams.
- Analyze test coverage and optimize DFT methodologies.
- Support silicon bring-up, failure analysis, and yield improvement activities.
Mandatory Skills
- Strong hands-on experience in:
- Scan Insertion
- ATPG
- MBIST
- JTAG / Boundary Scan
- DFT Verification
- Scan Compression
- Knowledge of ASIC/SOC design flow.
- Experience with synthesis and STA concepts.
- Good understanding of digital design fundamentals.
Preferred EDA Tools
- Synopsys DFT Compiler
- Tessent Scan / MBIST
- TetraMAX / TestMAX ATPG
- SpyGlass DFT
- Modus (Cadence)
Desired Candidate Profile
- Bachelor's/Master's Degree in Electronics/ECE/VLSI.
- Experience in ASIC/SOC development projects.
- Good debugging and problem-solving skills.
- Excellent communication and stakeholder management skills.
More Info
Key Skills
ASIC SOC design flow
digital design fundamentals
JTAG Boundary Scan
Scan Compression
STA concepts
DFT Verification
About Company
Skills:
boundary scan , Jtag, DFT verification, scan compression, Scan Insertion, DFT requirements, DFT simulation, pattern verification, MBIST, Cadence, DFT tool flows, DFT architecture, ATPG, gate-level simulation debug, silicon bring-up, Siemens EDA, Synopsys
Skills:
MBIST, ATPG, Dft, Scan Insertion, Siemens Tessent, DFT Simulation
Skills:
boundary scan , bist , Jtag, Debugging, physical design constraints, Sta, verification flows, ATE test pattern generation, compression techniques, MBIST, Analytical Skills, TetraMax, Synopsys DFT Compiler, DFT tools, Tessent, silicon bring-up, Scan ATPG, LBIST, RTL design synthesis
Skills:
Test Automation, DFT Techniques, Scan Insertion, ATPG Tools, Fault Simulation, Design Verification, RTL Coding, Debugging Skills, Timing Analysis, DFT Architecture
Skills:
Perl, Shell, Vcs, MBIST, MentorETVerify, ATPG, TestKompress, Modelsim