Jobs
Services
Career Solutions
Featured profileProfile highlighterCareer BoosterBest SellerResume WritingLinkedin Makeover
Prep
Interview Preparation
Career Advice
Please enter a job title/role/skill to search
Please enter a job title/role/skill to search
  • Fresher (< 1 year)

Search by job, company or skills

DFT Engineer
Mirafra Technologies

DFT Engineer

Mirafra Technologies
4-10 Years
Not Disclosed
  • Posted a day ago
  • Be among the first 10 applicants

Job Description

Role Overview

DFT Engineer

Experience- 4- 10 years

Location- Bangalore

Notice Period: 0 to 90day

Desired Skills and Experience:

Experienced in SCAN Insertion and Scan DRC fixing using Design Compiler or Fusion Compiler.

Experienced in ATPG Coverage Improvement, Fixing ATPG DRC's. Stuck-AT, At-Speed Pattern Generation using Tessent and TetraMax Tool.

MBIST Implementation with BIRA, BISR for different set of memory and test case generation on different algorithm's using Tessent MBIST(TMBIST) tool.

ATPG, MBIST TestBench Validation in unit Delay & across different timing corners. Debugging Simulation Mismatches using VCS, Verdi, NCSim. ModelSim Tool.

Basic skillset on awk, perl, shell scripting will be an advantage.

Indrakshi Kohli

Lead - Talent Acquisition |

[Confidential Information]

Mirafra Software Technologies Pvt. Ltd.

More Info

Job Type:
Permanent Job
Industry:
Semiconductor Manufacturing
Function:
DFT Engineering
Employment Type:
Full time

Key Skills

Design Compiler

Verdi

Fusion Compiler

BIRA

Tessent MBIST

TMBIST tool

NCSim

ATPG Coverage Improvement

Debugging Simulation Mismatches

MBIST Implementation

Tessent

test case generation

Stuck-AT At-Speed Pattern Generation

Scan DRC fixing

TetraMax Tool

BISR

Modelsim

ATPG MBIST TestBench Validation

Scan Insertion
perl
Vcs
shell scripting
Awk
Last Updated: 27-10-2026 05:21:49 PM

Similar Jobs

Design-For-Test (DFT) EngineerAccenture
A
3-5 yrs
Bengaluru, India
Skills:
Built-In Self-Test (BIST) implementation, Design for Testability (DFT), boundary scan standards, scan chain insertion and optimization techniques, silicon debug and failure analysis processes
Principal DFT Engineer ( Scan / ATPG)Ampere
6-8 yrs
Bengaluru, India
Skills:
SSN LBIST, MBIST insertion simulation and debug on RTL and gates netlist, Verilog Hdl, At-Speed LBIST coverage analysis, STA DFT Test mode timing constraint development and analysis, Simulators and waveform debugging tools, Scan ATPG with SSN Stuck-At, Scripting with Perl Tcl, ATE silicon debug, Simulation and debug, Scan insertion with compression, Boundary Scan insertion simulation and verification
DFT EngineerCapgemini
C
12-14 yrs
Bengaluru, India
Skills:
Synthesis, ASIC SOC design flow, Scan Insertion, digital design fundamentals, JTAG Boundary Scan, ATPG, Scan Compression, MBIST, STA concepts, DFT Verification
Sr. DFT - EngineerSEMI FIVE
2-8 yrs
Bengaluru, India
Skills:
boundary scan , Perl, Python, Sta, Scan Insertion, SDC constraints, MBIST, Physical design flows, Verification, Rtl Design, SpyGlass DFT rules, Synthesis, JTAG protocols, ATPG pattern generation, Hierarchical DFT
Senior DFT Engineerrecrew ai
7-9 yrs
Bengaluru, India
Skills:
Gate Level Simulations, stuck-at transition, Scan Insertion, memory repair solutions, MBIST, JTAG boundary scan, bridge path delay, DFT architecture, EDA Tools, DRC, IEEE 1149.1, ATPG pattern generation, scan chain stitching, DFT rule checks