DFT Engineer
DFT Engineer
Globex Digital Corp- Posted 3 months ago
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Job Description
Role - DFT Engineer
Experience - 7+years
Location - Bangalore and Chennai
Key Responsibilities:
- Interface with ASIC design teams to ensure DFT design rules and coverages are met.
- Generate high-quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques.
- MBIST verification (including repair), test pattern generation through Mentor tool.
- ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations.
- Work with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.
- Responsible for supporting post-silicon debug effort, issue resolution.
- Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE.
- Developing, enhancing and maintaining scripts as necessary.
Preferred Experience:
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering
- 7 to 15 years experience in ASIC/DFT - simulation and Silicon validation.
- Should have worked in at least one Full chip DFT
- Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement.
- In-depth knowledge and hands-on experience in ATPG - coverage analysis.
- In-depth knowledge of Memory verification, repair and failure root-cause analysis.
- Experience with any of these tools is required: ATPG - TestKompress, MBIST - MentorETVerify, Simulation - VCS (preferred), ModelSim.
- Expertise in scripting languages such as Perl, shell, etc. is an added advantage.
- Ability to work in an international team, dynamic environment with good communication skills.
- Ability to learn and adapt to new tools, methodologies.
- Ability to do multi-tasking & work on several high-priority designs in parallel.
More Info
About Company
Skills:
SSN LBIST, MBIST insertion simulation and debug on RTL and gates netlist, Verilog Hdl, At-Speed LBIST coverage analysis, STA DFT Test mode timing constraint development and analysis, Simulators and waveform debugging tools, Scan ATPG with SSN Stuck-At, Scripting with Perl Tcl, ATE silicon debug, Simulation and debug, Scan insertion with compression, Boundary Scan insertion simulation and verification
Skills:
boundary scan , Jtag, DFT verification, scan compression, Scan Insertion, DFT requirements, DFT simulation, pattern verification, MBIST, Cadence, DFT tool flows, DFT architecture, ATPG, gate-level simulation debug, silicon bring-up, Siemens EDA, Synopsys
Skills:
Synthesis, ASIC SOC design flow, Scan Insertion, digital design fundamentals, JTAG Boundary Scan, ATPG, Scan Compression, MBIST, STA concepts, DFT Verification
Skills:
test case generation , perl, Vcs, shell scripting, Awk, Design Compiler, Verdi, Fusion Compiler, BIRA, Tessent MBIST, TMBIST tool, NCSim, ATPG Coverage Improvement, Debugging Simulation Mismatches, MBIST Implementation, Tessent, Stuck-AT At-Speed Pattern Generation, Scan DRC fixing, TetraMax Tool, BISR, Modelsim, ATPG MBIST TestBench Validation, Scan Insertion
Skills:
boundary scan , Perl, Python, Sta, Scan Insertion, SDC constraints, MBIST, Physical design flows, Verification, Rtl Design, SpyGlass DFT rules, Synthesis, JTAG protocols, ATPG pattern generation, Hierarchical DFT