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DFT Engineer
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- Posted a month ago
- Over 50 applicants have applied
Job Description
Role : DFT Engineer
Exp : 5+ Years
Work Location : Bangalore
Industry : Semiconductor
Description
We are seeking an experienced DFT Engineer to join our team in India. The ideal candidate will have a strong background in design for test methodologies and will be responsible for ensuring the testability of our digital designs.
Responsibilities
- Develop and implement DFT methodologies for various projects.
- Create DFT test plans and strategies for new designs.
- Collaborate with design teams to ensure DFT requirements are met from the initial stages.
- Perform DFT analysis and simulations to validate designs.
- Conduct ATPG (Automatic Test Pattern Generation) and fault simulation.
- Work on scan chain insertion and testability analysis.
- Support chip bring-up and debugging efforts during validation phases.
Skills and Qualifications
- 5-12 years of experience in DFT (Design for Test) engineering.
- Strong knowledge of DFT concepts including scan, BIST (Built-In Self-Test), and JTAG.
- Experience with DFT tools such as Synopsys DFT Compiler, Mentor Graphics, or Cadence tools.
- Proficient in digital design and verification methodologies.
- Solid understanding of VLSI design flow and semiconductor technology.
- Familiarity with RTL design languages such as Verilog or VHDL.
- Ability to work collaboratively in a team environment and communicate effectively.
More Info
Key Skills
DFT Techniques
ATPG Tools
Debugging Skills
DFT Architecture
About Company
Skills:
Built-In Self-Test (BIST) implementation, Design for Testability (DFT), boundary scan standards, scan chain insertion and optimization techniques, silicon debug and failure analysis processes
Skills:
SSN LBIST, MBIST insertion simulation and debug on RTL and gates netlist, Verilog Hdl, At-Speed LBIST coverage analysis, STA DFT Test mode timing constraint development and analysis, Simulators and waveform debugging tools, Scan ATPG with SSN Stuck-At, Scripting with Perl Tcl, ATE silicon debug, Simulation and debug, Scan insertion with compression, Boundary Scan insertion simulation and verification
Skills:
Scan Compression Techniques, Fault Models, DFT Tools, Sign-Off, Scripting Automation, DFT Implementation, Boundary Scan IEEE 1149.1, Test Coverage Optimization, Post-Silicon Validation
Skills:
Synthesis, ASIC SOC design flow, Scan Insertion, digital design fundamentals, JTAG Boundary Scan, ATPG, Scan Compression, MBIST, STA concepts, DFT Verification
Skills:
test case generation , perl, Vcs, shell scripting, Awk, Design Compiler, Verdi, Fusion Compiler, BIRA, Tessent MBIST, TMBIST tool, NCSim, ATPG Coverage Improvement, Debugging Simulation Mismatches, MBIST Implementation, Tessent, Stuck-AT At-Speed Pattern Generation, Scan DRC fixing, TetraMax Tool, BISR, Modelsim, ATPG MBIST TestBench Validation, Scan Insertion