DFT Senior Engineer
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Job Description
Hiring for DFT Senior Engineer 9+ years
Looking for an experienced DFT Engineer with 9+ years of industry experience in ASIC/SoC Design for Test (DFT) implementation and validation. The candidate will be responsible for architecting, implementing, and verifying DFT solutions for complex SoCs.
Key Responsibilities
- Define and implement DFT architecture for complex SoCs.
- Integrate and verify Scan, MBIST, Boundary Scan (JTAG), and compression logic.
- Perform DFT rule checks, ATPG pattern generation, and pattern validation.
- Analyze test coverage, debug coverage issues, and drive closure.
- Develop and maintain DFT flows, scripts, and automation.
- Support post-silicon bring-up and production testing activities.
- Work closely with RTL, Verification, Physical Design, and Product Engineering teams.
- Ensure successful DFT sign-off and tape-out readiness.
Mandatory Skills
9+ years of hands-on DFT experience
Strong expertise in:
- Scan Insertion and Scan Compression
- ATPG and Fault Coverage Analysis
- MBIST Implementation and Verification
- JTAG / IEEE 1149.1
- DFT DRC and Debug
- SoC-level DFT Integration
Educational Qualification
- B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, or related disciplines.
Notice period : Any
Location: Open to discuss
Interested candidates can share their updated resume along with the following details:
- Name
- Contact
- Email id
- Current Company
- Total Experience
- Relevant DFT Experience
- Current CTC
- Expected CTC
- Notice Period / LWD
- Current Location
- Preferred Location
Email: [Confidential Information]
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
DFT DRC
DFT architecture
MBIST Implementation
SoC-level DFT Integration
Fault Coverage Analysis
Scan Compression
JTAG IEEE 1149.1
About Company
Skills:
simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, leading DFT activities, IP integration, DFT specification definition, SoC cycles, silicon debug activities
Skills:
Gate Level Simulations, stuck-at transition, Scan Insertion, memory repair solutions, MBIST, JTAG boundary scan, bridge path delay, DFT architecture, EDA Tools, DRC, IEEE 1149.1, ATPG pattern generation, scan chain stitching, DFT rule checks
Skills:
Python, Clp, Tcl, Perl, JTAG BSCAN, MBIST, LEC, SoC DFT Architecture, Logic and DRC analysis, P1500 implementation, ZERO delay and SDF based scan, ATPG DRC analysis, Memory BIST implementation, Hybrid-TK Compression, LPCT, Stuck at TDF, Scan Insertion, power analysis methodologies, Test coverage debug, JTAG simulations, Bridging Cell-aware iddq fault models, LBIST, iJTAG
Skills:
Dft, SSN, Simulation, Synopsys, Scan Insertion, Memory BIST, ATPG, DRC Coverage, Sms, pdl, IJTAG, ICL, Debug, occ, TetraMax
Skills:
retargeting , boundary scan , DFT architecture, pattern generation validation, MBIST, EDT OCC integration, Boundary Scan JTAG, Scan Architecture, IJTAG, DFT implementation debug, scan implementation, Memory IP Test Simulations